This invention relates to semiconductor memory devices and more particularly to an MOS ROM which is electrically erasable and/or electrically programmable.
Nonvolatile semiconductor memory devices are those in which the information stored is not lost when the power supply is removed. The classic example of a nonvolatile memory is the MOS ROM wherein the stored information is permanently fixed upon manufacture by the gate level mask or moat mask as set forth in U.S. Pat. No. 3,541,543, assigned to Texas Instruments, as widely used in calculators and microprocessor systems to store programs. However, it is preferable to be able to program the ROM devices after manufacture rather than during manufacture, so that no unique masks are required. Various electrically programmable ROM devices have been developed such as that shown in U.S. Pat. No. 3,984,822 which employs a floating gate in a double level polysilicon MOS ROM; the floating gate is charged by injection of electrons from the channel, and remains charged even when no power supplies are present. Other devices of this type have employed charge storage on a nitride-oxide interface. Even though the devices are electrically programmable, some are not electrically alterable or deprogrammable (except by exposing the semiconductor chip to ultraviolet light, for example). Electrically alterable ROM's have been developed as set forth in U.S. Pat. Nos. 3,881,180, issued Apr. 29, 1975, and 3,882,469, issued May 6, 1975, as well as application Ser. No. 644,982, filed Dec. 29, 1975, all by M. W. Gosney and assigned to Texas Instruments; the Gosney devices are floating gate cells with dual injection (both holes and elctrons) so that the gates may be charged or discharged. Prior cells have exhibited some undesirable characteristic such as large cell size, process incompatible with standard techniques, high voltages needed for programming, low yields due to close parametric dependency of critical voltage levels, etc.
In copending application Ser. No. 754,207, filed Dec. 27, 1976, by David J. McElroy, assigned to Texas Instruments, an electrically erasable floating gate memory device is described which employs a series enhancement transistor to eliminate the undesirable effect of the floating gate cell going into depletion mode when erased; in the McElroy device, constraints on the erase voltages are reduced so yields are increased and the electrical specifications are improved. However, threshold voltage of the series enhancement device will be dictated by the P+ tank doping, for a given gate oxide thickness. For proper programming, the P+ tank must have a surface concentration of 1 to 2.times.10.sup.16 /cc, causing the threshold voltage of the series enhancement device to be +2 to +3 v. with typical gate oxide thickness. Particularly for devices using a single +5 v. supply, it is preferable that the threshold be lower, about +1 or +0.8 v., but at the same time additional masking steps are undersirable as the yield decreases for each mask step added so costs go up.
It is therefore the principal object of the invention to provide an improved electrically programmable and electrically alterable semiconductor memory cell, particularly a cell with improved electrical specifications. Another object is to provide an electrically alterable cell which is of small cell size when formed in a semiconductor integrated circuit. A further object is to provide a process for making electrically alterable memory cells compatible with N-channel silicon gate technology and of high yield and lost cost.